The present invention relates to verification assistance for digital circuit designs.
In the development of digital circuits, the largest fraction of design time is usually spent on detecting design flaws. For the analysis of the functional behavior of the design of digital circuits, circuit designers review verification data. In this context, verification data are data used for verification and, in particular, the verification of digital circuits. The verification data can include messages or entries in a database, which can be presented as a list and displayed on a monitor. The verification data typically include trace data generated by trace programs and/or debug data generated by debug programs. Trace programs log signal values or events of interest in digital circuit designs and/or derive further information from signal values or events of interest during the simulation of the digital circuits. Thus, trace data usually refer to simulation data obtained by the simulation of a digital circuit. Debug programs compare simulation data obtained by the simulation of a digital circuit to reference data. Thus, debug data usually refer to the comparison of simulation data and reference data. In U.S. Pat. No. 8,121,825, US 2012/0179447, US 2009/0248390, US 2011/024831, U.S. Pat. No. 6,618,839, U.S. Pat. No. 6,885,983, U.S. Pat. No. 7,367,001 various trace and debug programs are disclosed.
The amount of verification data for a digital circuit design can be very large. Usually only a small fraction of the verification data is useful for the identification of design flaws. In practice, a large proportion of the time spent in verification of a digital circuit design is spent on finding the useful verification data. The useful verification data can often be identified by the content and the interlinkage to other verification data. According to the preamble of its claim 1, U.S. Pat. No. 7,200,588 discloses a verification assistance method for the design of digital circuits that enables the selection of verification data to be displayed on a monitor for review by circuit designers, thereby alleviating the handling of a huge amount of verification data. However, this verification assistance method does not support the circuit designers in selecting useful verification data to be displayed for review so that it is likely that the circuit designers actually select useless verification data to be displayed. Therefore, the verification assistance method may not considerably reduce the time and effort spent on spotting design flaws.